The active switching elements of integrated circuits are interconnected by metal lines deposited by various methods such as physical vapor deposition, chemical vapor deposition and evaporation. Typically, several levels of metal lines are used in an integrated circuit to allow crossovers. At certain locations, electrical contact is made between lines of different levels. Such locations are called vias.
The drive of integrated circuits to submicron geometry results in vias of extreme aspect ratio and size. Processes used to define those vias do not allow For the reliable control of via sidewalls. Undercut or sloped re-entrant profiles are often observed. Wafers which show such profiles have to be discarded because reliable interconnections through those vias are not possible, thus effecting wafer line yield.
The most commonly used interconnecting metal for high aspect ratio vias is the tungsten plug deposited by the decomposition of tungsten hexafluoride on the sidewall of the via. Such plugs are formed by either selective deposition which has not been reliable enough to be used for manufacturing purposes or by the blanket deposition of a film with successive etch back. All tungsten depositions require the prior deposition of an adhesive layer which is typically a layer of plasma vapor deposited titanium nitride. The titanium nitride deposition may result in a re-entrant profile particularly on geometries with high aspect ratios. The resulting chemical vapor deposition then shows the well known keyhole which results in integrated circuit reliability problems and limits the use of tungsten chemical vapor deposition to critical geometries of greater than 0.5 microns.
In addition to the process difficulties, tungsten chemical vapor deposition processes are complex and expensive. Due to the high resistivity of tungsten, material contact resistances and via resistance are high and can limit the performance of integrated circuits.
The use of aluminum as a material for filling interconnecting vias between integrated circuit metal lines and between the first layer of metal and the semiconductor surface has been proposed utilizing surface diffusion to move materials into the via at temperatures of approximately 450.degree. C. This is disclosed, for example, in Armstrong U.S. Pat. No. 4,994,162. This uses a low temperature seed layer providing a continuous high quality diffusion path for subsequently deposited material to diffuse along. A high temperature low deposition rate step to allow efficient surface diffusion into the feature is employed followed by a high temperature high deposition rate step to complete the deposition.
This process requires a continuous diffusion path along the sidewall of the via and is dependent on achieving certain process conditions simultaneously. These conditions are sometimes difficult to achieve and control.
Bulk diffusion as a mechanism for via filling has been proposed by Sugano et al in the 1992 VMIC Conference Proceedings "Quarter Micron Whole Filling With SiN Sidewalls By Aluminum High Temperature Sputtering." With the Sugano process, the driving force for via filling is the interface between a titanium surface layer and the deposited aluminum. This process requires the presence of a continuous and high quality titanium surface layer on the sidewall of a via.
Tracy U.S. Pat. No. 4,970,176 discloses deposition of a relatively thick layer of aluminum at a first temperature and a subsequent deposition of a thin layer of aluminum at a higher temperature. The specification indicates that the temperature increase acts to reflow the aluminum through grain growth and recrystallization. As shown from the specification, the filling of the via starts from the bottom of the via and works up to the top. At the time the Tracy application was filed, typically the vias were of a size greater than one micron.
Inoue U.S. Pat. No. 5,071,791 discloses heating a substrate water while depositing aluminum and subsequent rapid freezing in order to avoid silicon formation that can precipitate from the aluminum. Basically this is a bulk diffusion process. Further, Kamoshida U.S. Pat. No. 4,816,126 discloses bias deposition of aluminum film. And, Wang U.S. Pat. No. 5,108,570 discloses sputter coating an initial layer of 2000 angstroms and a subsequent layer at a higher temperature for about 30 to 45 seconds. The background indicates that the vias can be as small as 1.5 microns. None of these patents disclose methods which would be effective to fill submicron vias having aspect ratios greater than 1. Further, these methods are generally relatively complex requiring critical control of reaction conditions.